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HI-303
Data Sheet August 2003 FN3125.9
Dual, SPDT CMOS Analog Switch
The HI-303 switch is a monolithic device fabricated using CMOS technology and the Intersil dielectric isolation process. This switch features break-before-make switching, low and nearly constant ON resistance over the full analog signal range, and low power dissipation. The HI-303 is TTL compatible and has a logic "0" condition with an input less than 0.8V and a logic "1" condition with an input greater than 4V. (See pinouts for switch conditions with a logic "1" input.)
Features
* Analog Signal Range (15V Supplies) . . . . . . . . . . 15V * Low Leakage at 25oC . . . . . . . . . . . . . . . . . . . . . . . 40pA * Low Leakage at 125oC . . . . . . . . . . . . . . . . . . . . . . . 1nA * Low On Resistance at 25oC . . . . . . . . . . . . . . . . . . . 35 * Break-Before-Make Delay . . . . . . . . . . . . . . . . . . . . 60ns * Charge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pC * TTL, CMOS Compatible * Symmetrical Switch Elements
Ordering Information
PART NUMBER HI1-0303-2 HI1-0303-5 HI3-0303-5 HI9P0303-9 TEMP. RANGE (oC) -55 to 125 0 to 75 0 to 75 -40 to 85 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC PKG. DWG. # F14.3 F14.3 E14.3 M14.15
* Low Operating Power (Typ) . . . . . . . . . . . . . . . . . . . . 1.0mW
Applications
* Sample and Hold (i.e., Low Leakage Switching) * Op Amp Gain Switching (i.e., Low On Resistance) * Portable, Battery Operated Circuits * Low Level Switching Circuits
Functional Diagram
S IN N P D
* Dual or Single Supply Systems
Pinout
Switch States Shown For A Logic "1" Input HI-303 (PDIP, CERDIP, SOIC) TOP VIEW
NC 1 S3 2 D3 3 D1 4 S1 5 IN1 6 GND 7 14 V+ 13 S4 12 D4 11 D2 10 S2 9 IN2 8 V-
LOGIC 0 1
SW1, SW2 OFF ON
SW3, SW4 ON OFF
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HI-303 Schematic Diagrams
A V+ MN1B
MN2B MP5B IN MP4B
MN3B
OUT MN4B MN6B
MP3B
MP2B MP1B V-
A SWITCH CELL
V+ D2A 200 LOGIC IN D1A GND VSWITCH CELL DRIVER (ONE PER SWITCH CELL) DIGITAL INPUT BUFFER AND LEVEL SHIFTER MN1A MN2A MN3A MN4A MN5A MN6A MN7A MN8A A A MP1A MP2A MP3A MP4A MP5A MP6A MP7A MP8A
2
HI-303
Absolute Maximum Ratings
Voltage Between Supplies (V+ to V-) . . . . . . . . . . . . . . . 44V (22V) Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . (V+) +4V to (V-) -4V Analog Input Voltage . . . . . . . . . . . . . . . . . . (V+) +1.5V to (V-) -1.5V Typical Derating Factor . . . . . . . . . 1.5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 80 24 PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 120 N/A Maximum Junction Temperature Ceramic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range HI-303-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HI-303-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC HI-303-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. Unless Otherwise Specified TEMP (oC) -2 MIN TYP MAX MIN -5, -9 TYP MAX UNITS
PARAMETER DYNAMIC CHARACTERISTICS Switch ON Time, tON Switch OFF Time, tOFF Break-Before-Make Delay, tOPEN Charge Injection Voltage, V (Note 7) OFF Isolation (Note 6) Input Switch Capacitance, CS(OFF) Output Switch Capacitance, CD(OFF) Output Switch Capacitance, CD(ON) Digital Input Capacitance, CIN DIGITAL INPUT CHARACTERISTICS Input Low Level, VINL Input High Level, VINH (Note 10) Input Leakage Current (Low), IINL (Note 5) Input Leakage Current (High), IINH (Note 5) ANALOG SWITCH CHARACTERISTICS Analog Signal Range ON Resistance, rON (Note 2)
25 25 25 25 25 25 25 25 25
-
210 160 60 3 60 16 14 35 5
300 250 -
-
210 160 60 3 60 16 14 35 5
300 250 -
ns ns ns mV dB pF pF pF pF
Full Full Full Full
4 -
-
0.8 1 1
4 -
-
0.8 1 1
V V A A
Full 25 Full
-15 -
35 40 0.04 1 0.04 1 0.03 0.5
+15 50 75 1 100 1 100 1 100
-15 -
35 40 0.04 0.2 0.04 0.2 0.03 0.2
+15 50 75 5 100 5 100 5 100
V nA nA nA nA nA nA
OFF Input Leakage Current, IS(OFF) (Note 3)
25 Full
OFF Output Leakage Current, ID(OFF) (Note 3)
25 Full
ON Leakage Current, ID(ON) (Note 4)
25 Full
3
HI-303
Electrical Specifications
Supplies = +15V, -15V; VIN = Logic Input. VIN - for Logic "1" = 4V, for Logic "0" = 0.8V. Unless Otherwise Specified (Continued) TEMP (oC) -2 MIN TYP MAX MIN -5, -9 TYP MAX UNITS
PARAMETER POWER SUPPLY CHARACTERISTICS Current, I+ (Note 8)
25 Full
-
0.09 0.01 0.01 0.01 -
0.5 1 10 100 10 100 10 100
-
0.09 0.01 0.01 0.01 -
0.5 1 100 100 100 -
mA mA A A A A A A
Current, I- (Note 8)
25 Full
Current, I+ (Note 9)
25 Full
Current, I- (Note 9)
25 Full
NOTES: 2. VS = 10V, IOUT = 10mA. On resistance derived from the voltage measured across the switch under these conditions. 3. VS = 14V, VD = 14V. 4. VS = VD = 14V. 5. The digital inputs are diode protected MOS gates and typical leakages of 1nA or less can be expected. 6. VS = 1VRMS , f = 500kHz, CL = 15pF, RL = 1K. 7. VS = 0V, CL = 10nF, Logic Drive = 5V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = CL x V. 8. VIN = 4V (one input, all other inputs = 0V). 9. VIN = 0.8V (all inputs). 10. To drive from DTL/TTL circuits, pullup resistors to +5V supply are recommended.
Test Circuits and Waveforms
15V S VS = +3V RL 300 LOGIC INPUT GND V-15V 90% 0V SWITCH OUTPUT tOFF tON 10% V+ D VO CL 33pF SWITCH OUTPUT LOGIC INPUT 0V VS LOGIC "1" = SWITCH ON VINH 50% 50%
SWITCH TYPE HI-303
VINH 4V
FIGURE 1A. TEST CIRCUIT FIGURE 1. SWITCH tON AND tOFF
FIGURE 1B. MEASUREMENT POINTS
4
HI-303 Test Circuits and Waveforms
(Continued)
LOGIC INPUT (V)
+15V V+ RGEN = 0 S D RL 10k CL 10pF
6 4 2 0 LOGIC INPUT
VGEN
IN
VVLOGIC GND -15V 0 0.4 0.8 TIME (s) 1.2 1.6
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. TTL LOGIC INPUT
OUTPUT VOLTAGE (V)
10 5 0 VGEN = 10V
(NOTE 11)
OUTPUT VOLTAGE (V)
5 0 VGEN = 5V
0
0.4
0.8 TIME (s)
1.2
1.6
0
0.4
0.8 TIME (s)
1.2
1.6
FIGURE 2C. VANALOG = 10V
FIGURE 2D. VANALOG = 5V
OUTPUT VOLTAGE (V)
5 0 -5 VGEN = 0V
OUTPUT VOLTAGE (V)
0 -5 VGEN = -5V
0
0.4
0.8 TIME (s)
1.2
1.6
0
0.4
0.8 TIME (s)
1.2
1.6
FIGURE 2E. VANALOG = 0V
FIGURE 2F. VANALOG = -5V
5
HI-303 Test Circuits and Waveforms
(Continued)
OUTPUT VOLTAGE (V)
0 -5 -10 VGEN = -10V 0 0.4 0.8 TIME (s) 1.2 1.6
FIGURE 2G. VANALOG = -10V NOTE: 11. If RGEN , RL or CL is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 2. SWITCHING WAVEFORMS FOR VARIOUS ANALOG INPUT VOLTAGES
15V S1 VS1 = +3V VS2 = +3V S2
V+
D1 D2
OUT 1 OUT 2
LOGIC INPUT 0V
LOGIC "1" = SWITCH ON VINH
RL1 = RL2 = 300 CL1 = CL2 = 33pF
RL2 LOGIC INPUT GND V-15V
CL2
RL1
CL1 0V SWITCH OUTPUTS 50% 0V
50%
50% OUT 1 OUT 2 50% tOPEN
SWITCH TYPE HI-303
VINH 5V
tOPEN
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE DELAY (tOPEN)
Typical Performance Curves
80 DRAIN TO SOURCE ON RESISTANCE () DRAIN TO SOURCE ON RESISTANCE () V+ = +15V, V- = -15V 80 TA = 25oC D
60 125oC 25oC -55oC
60
C
40
40
B A
20
20
A B C D
V+ = +15V, V- = -15V V+ = +10V, V- = -10V V+ = +7.5V, V- = -7.5V V+ = +5V, V- = -5V -10 -5 0 5 10 15
0 -15
-10
-5
0
5
10
15
0 -15
DRAIN VOLTAGE (V)
DRAIN VOLTAGE (V)
FIGURE 4. rDS(ON) vs VD
FIGURE 5. rDS(ON) vs VD
6
HI-303 Typical Performance Curves
100 V+ = +15V, V- = -15V TA = 25oC, VS = 15V, RL = 2K POWER DISSIPATION (mW) 80 OFF ISOLATION (dB) 10 RL = 100 60 RL = 1k 40
(Continued)
100 V+ = +15V, V- = -15V CLOAD = 30pF, VS = 1VRMS
1.0
20
0.1 1 10 100 1K 10K 100K 1M LOGIC SWITCHING FREQUENCY (50% DUTY CYCLE) (Hz)
0 105
106
107
108
FREQUENCY (Hz)
FIGURE 6. DEVICE POWER DISSIPATION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT)
10.0 V+ = +15V, V- = -15V
FIGURE 7. OFF ISOLATION vs FREQUENCY
10.0
V+ = +15V, V- = -15V | VD | = | VS | = 14V
SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
1.0 ID(ON) (nA) 0.1
1.0
0.1
0.01 25 75 125 TEMPERATURE (oC)
0.01 25
75
125
TEMPERATURE (oC)
FIGURE 8. IS(OFF) OR ID(OFF) vs TEMPERATURE*
FIGURE 9. ID(ON) vs TEMPERATURE*
* The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit.
60 OUTPUT ON CAPACITANCE (pF)
16
INPUT CAPACITANCE (pF)
50
12
40
8
TRANSITION (INDETERMINATE DUE TO ACTIVE INPUT)
30
4
20 0 2 4 6 8 10 12 14 16 DRAIN VOLTAGE (V)
0
2
4
6
8
10
12
14
16
INPUT VOLTAGE (V)
FIGURE 10. OUTPUT ON CAPACITANCE vs DRAIN VOLTAGE
FIGURE 11. DIGITAL INPUT CAPACITANCE vs INPUT VOLTAGE
7
HI-303 Typical Performance Curves
300 V+ = +15V, V- = -15V VINH = 4.0V, VINL = 0V SWITCHING TIME (ns) tON 200 SWITCHING TIME (ns) 300 V+ = +15V, TA = 25oC VINH = 4V, VINL = 0V
(Continued)
tON
200
tOFF
tOFF 100
100
-55
-35
-15
5
25
45
65
85
105
125
0
5
10
15
TEMPERATURE (oC)
NEGATIVE SUPPLY (V)
FIGURE 12. SWITCHING TIME vs TEMPERATURE
FIGURE 13. SWITCHING TIME vs NEGATIVE SUPPLY VOLTAGE
SWITCHING TIME/BREAK-BEFORE-MAKE TIME (s)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 tOPEN ONLY tOFF
INPUT SWITCHING THRESHOLD (V)
V- = -15V, TA = 25oC VINH = 4.0V, VINL = 0V
7 V- = -15V, TA = 25oC 6 5 4 3 2 1 0
tON
10
15
0
5
10
15
POSITIVE SUPPLY VOLTAGE (V)
POSITIVE SUPPLY VOLTAGE (V)
FIGURE 14. SWITCHING TIME AND BREAK-BEFORE-MAKE TIME vs POSITIVE SUPPLY VOLTAGE
FIGURE 15. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTAGE
8
HI-303 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
-C-
A2 B B1 C D D1 E E1 e eA eB L N
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
0.100 BSC 0.300 BSC 0.115 14 0.430 0.150 -
2.54 BSC 7.62 BSC 10.92 3.81 14
2.93
9
HI-303 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
c1 D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
10
HI-303 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E

A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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